BICMOS integrated circuits incorporate bipolar transistors for functions requiring relatively high drive current, while still achieving the relatively high density and low power consumption available from CMOS technology.
The specific problem to which the invention can be applied is a gate array memory cell that does not require a complicated sense amp, and has sufficient drive current capability to permit a relatively large number of rows for each read bitline. Ideally, the memory cell would use a minimum number of transistors.
BICMOS gate arrays include base cells with a predetermined number of bipolar and CMOS transistors. For example, the TGB1000 Gate Array manufactured by Texas Instruments Incorporated includes a base cell with 18 transistors: six p-channel, ten n-channel, and two NPN.
FIGS. 1a and 1b illustrate two typical dual-port dual-invertor memory cell configurations such as might be implemented in a gate array base cell like that of the TGB1000. The memory cell in FIG. 1a uses eight CMOS transistors, including a two-transistor WRITE and READ transmission gates--it is disadvantageous in that it requires a relatively complicated sense amp and uses four vertical routing channels. The memory cell in FIG. 1b uses eleven CMOS transistors, and includes an output driver circuit--it is disadvantageous in that it has a relatively low drive capability (thereby limiting the number of rows on the read bitline).
In both cases, moreover, only one memory cell can be implemented in a single TGB1000 base cell--both configurations use six of the available ten n-channel transistors.
Accordingly, a need exists for a memory cell configuration that does not require a complicated sense amp, and has sufficient drive to permit a relatively large number of rows of memory cells for each read bitline.